The present invention relates to a method for fabricating trenches for storage capacitors of DRAM semiconductor memories by plasma etching semiconductor substrates.
In the case of storage capacitors for DRAM semiconductor memories in the form of trench capacitors, as the integration level increases, less and less area is available, that is to say the cross-sectional area or the diameter of the capacitor trenches in the semiconductor substrate inevitably decreases. One possibility for realizing a predetermined capacitance, typically about 45 fF, is to increase the trench depth accordingly.
Trenches are typically fabricated by plasma etching in the semiconductor substrate. If that is the case, limits are necessarily encountered in connection with increasing the trench depth of storage capacitors with an increasing integration level of DRAM semiconductor memories, for example a storage capacity of 256 Mbits.
That is because, on one hand, during plasma etching, the etching rate decreases as the etching depth increases because fewer and fewer reactive particles reach the progressively deeper bottom of the trench structure. That becomes more pronounced with an increasing ratio of depth to width, the so-called aspect ratio, of the trench structure. On the other hand, side wall passivation films produced in the course of etching increase the aspect ratio even further, which additionally intensifies the decrease in the etching rate. The two effects mentioned above lead to the etching being slowed down, and thus to the process duration being prolonged, which in turn leads to a considerable increase in process costs.
Furthermore, depending on the process control, the etching ultimately comes to a complete standstill in the event of very large aspect ratios, so that fundamental limits are imposed on arbitrarily increasing the trench depth in a plasma etching process.
A special case in connection with increasing the trench depth is the fabrication of trenches with slightly bulged profiles in the lower region of the trench. However, that enables only very limited increases in capacitance.
The problems outlined above can be countered by using dielectrics having a larger dielectric constant such as e.g. titanium dioxide, instead of customary capacitor dielectrics such as, for example, silicon dioxide, oxide nitrides or oxide-nitride and oxide-nitride-oxide sandwich structures. However, it is not certain whether extremely high demands that are to be made of a CVD deposition method with regard to conformity of the deposited layers can be fulfilled in that case, in particular with trench structures having a large aspect ratio.
European Patent Application 0 553 791 A1 discloses increasing the capacitance of capacitors of the type under discussion without increasing the aspect ratio. That is done by rendering their lower electrode, that is to say that surface of the semiconductor substrate which forms the trench surface, porous by roughening. The roughening can be effected, for example, by anodic oxidation, wet etching or dry etching.
The porosity produced by the roughening process constitutes microdepressions, which signifies an area enlargement and thus an increase in capacitance, with the aspect ratio remaining the same. It is clear that only a comparatively limited area enlargement and thus increase in capacitance can be realized by a method of that type.
It is accordingly an object of the invention to provide a method for fabricating trenches for storage capacitors of DRAM semiconductor memories, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known methods of this general type and with which, by virtue of a comparatively considerable area enlargement of a trench surface, a correspondingly considerable increase in a capacitance of storage capacitors is possible.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating trenches for storage capacitors of DRAM semiconductor memories, which comprises fabricating a first partial trench region with a surface and with a cross-sectional profile deviating from an essentially constant cross-sectional profile toward a larger cross-sectional profile in a semiconductor substrate in a plasma etching step, by setting a predetermined ratio between an isotropic and an anisotropic etching component; passivating the surface of the first partial trench region; and continuing the etching and passivating k times periodically, where k denotes a predetermined integer, to fabricate further partial trench regions adjoining the first partial trench region in a trench course direction, until a predetermined overall trench depth has been reached.
In accordance with another mode of the invention, there is provided a method which further comprises carrying out the fabricating step by fabricating a convex cross-sectional profile as the cross-sectional profile deviating from an essentially constant cross-sectional profile.
In accordance with a further mode of the invention, there is provided a method which further comprises setting the ratio of isotropic to anisotropic etching component in the plasma etching step according to predetermined process parameters.
In accordance with an added mode of the invention, there is provided a method which further comprises setting radio frequency power, pressure, magnetic field strength and/or process gas as a process parameter of the etching step to set the ratio of isotropic to anisotropic etching component.
In accordance with an additional mode of the invention, there is provided a method which further comprises using NF3, XeF2 or SF6 as an etching gas. In accordance with yet another mode of the invention, there is provided a method which further comprises passivating the surface of the partial trench regions by plasma polymerization in a plasma of polymer-forming gases. In accordance with yet a further mode of the invention, there is provided a method which further comprises using CnH2n+2 as a polymer-forming gas. In accordance with yet an added mode of the invention, there is provided a method which further comprises using CH4 as the polymer-forming gas. In accordance with yet an additional mode of the invention, there is provided a method which further comprises using CnH2n as a polymer-forming gas. In accordance with still another mode of the invention, there is provided a method which further comprises using CHF3, C2F6 or C4F8 as a polymer-forming gas.
In accordance with still a further mode of the invention, there is provided a method which further comprises concluding the periodic etching and passivating step, then producing an oxide on the trench surface by thermal growth and subsequently isotropically etching away the oxide.
In accordance with a concomitant mode of the invention, there is provided a method which further comprises carrying out the isotropic etching in a wet or dry etching process.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating trenches for storage capacitors of DRAM semiconductor memories, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.